EVAL-AD5533EB【PDF 14/16 页】32-Channel Precision Infinite Sample-and

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REV. A

–14–

AD5533B

readback, 16 bits of data are clocked out of the AD5533B on

each rising edge of SCLK and clocked into the DSP on the rising

edge of SCLK. D

is ignored. The valid 14 bits of data will be

centered in the 16-bit RX register when using this configuration.

The SPORT control register should be set up as follows:

TFSW

= RFSW = 1, Alternate Framing

INVRFS = INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right-Justify Data

ISCLK

= 1, Internal Serial Clock

TFSR

= RFSR = 1, Frame Every Word

IRFS

= 0, External Framing Signal

ITFS

= 1, Internal Framing Signal

SLEN

= 1001, 10-Bit Data-Words (ISHA Mode Write)

SLEN

= 1111, 16-Bit Data-Words (Readback Mode)

Figure 9 shows the connection diagram.

SCLK

AD5533B

OUT

SYNC

TFS

RFS

SCLK

ADSP-2101/

ADSP-2103

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 9. AD5533B to ADSP-2101/ADSP-2103 Interface

AD5533B to MC68HC11

The serial peripheral interface (SPI) on the MC68HC11 is config-

ured for master mode (MSTR = 1), clock polarity bit (CPOL) = 0

and the clock phase bit (CPHA) = 1. The SPI is configured by

writing to the SPI control register (SPCR)— see

68HC11 User

Manual

. SCK of the 68HC11 drives the SCLK of the AD5533B,

the MOSI output drives the serial data line (D

) of the AD5533B,

and the MISO input is driven from D

OUT

. The

SYNC

signal is

derived from a port line (PC7). When data is being transmitted to

the AD5533B, the

SYNC

line is taken low (PC7). Data appear-

ing on the MOSI output is valid on the falling edge of SCK.

Serial data from the 68HC11 is transmitted in 8-bit bytes with

only eight falling clock edges occurring in the transmit cycle.

Data is transmitted MSB first. In order to transmit 10 data bits

in ISHA mode it is important to left-justify the data in the SPDR

high and pulled low again before any further read/write cycles

can take place. A connection diagram is shown in Figure 10.

SCLK

AD5533B

OUT

SYNC

MISO

PC7

SCK

MC68HC11

ADDITIONAL PINS OMITTED FOR CLARITY

MOSI

Figure 10. AD5533B to MC68HC11 Interface

AD5533B to PIC16C6x/7x

The PIC16C6x synchronous serial port (SSP) is configured as an

SPI Master with the clock polarity bit = 0. This is done by writing

to the Synchronous Serial Port Control Register (SSPCON). See

PIC16/17 Microcontroller User Manual

. In this example I/O port

RA1 is being used to pulse

SYNC

and enable the serial port

of the AD5533B. This microcontroller transfers only eight bits of

data during each serial transfer operation; therefore, two consecu-

tive read/write operations are needed for a 10-bit write and a 14-bit

readback. Figure 11 shows the connection diagram.

SCLK

PIC16C6x/7x

OUT

SYNC

SCK/RC3

AD5533B

ADDITIONAL PINS OMITTED FOR CLARITY

SDO/RC5

SDI/RC4

RA1

Figure 11. AD5533B to PIC16C6x/7x Interface

AD5533B to 8051

The AD5533B requires a clock synchronized to the serial

data. The 8051 serial interface must therefore be operated in

Mode 0. In this mode, serial data enters and exits through RxD

and a shift clock is output on TxD. Figure 12 shows how the 8051

is connected to the AD5533B. Because the AD5533B shifts data

out on the rising edge of the shift clock and latches data in on

the falling edge, the shift clock must be inverted. The AD5533B

requires its data with the MSB first. Since the 8051 outputs

the LSB first, the transmit routine must take this into account.

8051

SCLK

OUT

SYNC

TXD

AD5533B

ADDITIONAL PINS OMITTED FOR CLARITY

RXD

P1.1

Figure 12. AD5533B to 8051 Interface

APPLICATION CIRCUITS

AD5533B in a Typical ATE System

The AD5533B infinite sample-and-hold is ideally suited for use

in automatic test equipment. Several ISHAs are required to

control pin drivers, comparators, active loads, and signal timing.

Traditionally, sample-and-hold devices with droop were used in

these applications. These required refreshing to prevent the voltage

from drifting.

The AD5533B has several advantages: no refreshing is required,

there is no droop, pedestal error is eliminated, and there is no

need for extra filtering to remove glitches. Overall, a higher level

of integration is achieved in a smaller area. See Figure 13.

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